System and method for mode register control of data bus operating mode and impedance

ABSTRACT

A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

TECHNICAL FIELD

The present invention relates generally to memory devices, and morespecifically to a system and method for allowing user selection of theoperating mode and input and output impedance of data bus terminals.

BACKGROUND OF THE INVENTION

In synchronous memory devices, such as synchronous dynamic random accessmemory (“SDRAM”) devices, the memory device is clocked by an externalclock signal to allow operations to be performed at predetermined timesrelative to the rising and falling edges of the applied clock signal.For example, write data signals are applied to data bus terminals of thememory device in synchronism with the external clock signal, and thememory device must latch these data signals at the proper times tosuccessfully capture the data signals. In the present description,“external” is used to refer to signals and operations outside of thememory device, and “internal” to refer to signals and operations withinthe memory device.

In a conventional SDRAM device, data drivers in the memory device mayoperate in either of two modes. In the first mode, known as the centertapped termination (“CTT”) mode, the memory devices biases the data busterminals to a voltage intermediate high and low voltages correspondingto logic levels between which the terminals are switched to output readdata signals. These high and low voltages are typically a supply voltageV_(CC) and ground, respectively, and the CTT termination voltage isV_(CC)/2. When read data signals are output from the memory device, thememory device drives the data bus terminals from V_(CC)/2 to eitherV_(CC) or ground depending on whether the corresponding read data bitsare “1” or “0,” respectively. When write data signals are to be appliedto the data bus terminals, the data bus terminals are biased toV_(CC)/2. The externally applied write data signals applied to the databus terminals drive the data bus terminals from V_(CC)/2 to eitherV_(CC) or ground depending on whether the corresponding write data bitsare “1” or “0,” respectively. One set of read data signals are generallyoutput from the memory device and one set of write data signals aregenerally applied to the memory device in synchronism with the risingedge of the clock signal. However, in double-data rate (“DDR”) memorydevices, one set of read data signals are output from the memory deviceand one set of write data signals are applied to the memory device insynchronism with both the rising edge and the falling edge of the clocksignal. When the memory device is inactive, the memory device does notbias the data bus terminals, but they are left at a high impedance andbiased to V_(CC)/2 by external circuitry.

In the other mode, known as the default high (“VDD”) mode, the data busterminals are biased to V_(CC) when data are to be either written to orread from the memory device. More specifically, the data bus terminalsare biased to V_(CC) during a preamble occurring before data are to beread from or written to the memory device, and during a postambleoccurring after data have been read from or written to the memorydevice. The duration of the preamble is typically one-clock period, andthe duration of the postamble is typically one-half clock period. Whenread data signals are output from the memory device, the data busterminals are driven from V_(CC) to ground if the corresponding readdata bits are “0.” If the corresponding read data bits are “1,” thevoltage at the data bus terminals remains at V_(CC). Write data signalsapplied to the data bus terminals drive the data bus terminals to groundif the corresponding write data bits are “0,” but maintain the data busterminals at V_(CC) if the corresponding write data bits are “1.” Again,when the memory device is inactive, the memory device does not bias thedata bus terminals, but they are left at a high impedance and biased toV_(CC) by external circuitry.

Another variation in the operating characteristics of memory device databus terminals is the input and output impedance of the terminals. Theinput impedance of the data bus terminals affects the amount of currentrequired to drive the data bus terminals to voltages corresponding tothe two logic levels as well as the switching characteristics of thedata bus terminals. Generally, a lower input impedance requires morecurrent to drive the data bus terminals high and low, but it allows theterminals to be switched at a faster rate. The output impedance of thedata bus terminals affects the “drive strength” of the memory device,i.e., the ability of the memory device to drive components connected tothe data bus terminals. Again, a lower output impedance can require morecurrent, but it can allow the data bus terminals to be switched at afaster rate.

In the past, the operating mode and input and output impedance of memorydevice data terminals were determined at the time memory devices weremanufactured, although in some cases, the operating mode and/orimpedance could be selected by opening or closing programmable linksduring manufacture. More recently, memory devices have been manufacturedwith an extended load mode register that includes an output drivestrength bit. The drive strength bit can be programmed so that read datadrivers operate in either a low impedance, full-drive mode or a highimpedance, reduced-drive mode of operation. A memory controllertypically sets the output drive strength bit in the extended load moderegister via a load mode register command to thereby place the datadriver in the desired operating mode. The data driver is typicallyplaced in the full-drive mode when the DDR SDRAM device is beingutilized in a conventional application, such as on a conventional memorymodule. The data driver may be placed in the reduced-drive mode when theDDR SDRAM device is being utilized in a point-to-point application, suchas on a graphics card. During the full-drive mode, the data driverprovides sufficient current to drive the DQ signals to full-rangevoltages for a particular loading of the data bus, while during thereduced-drive mode the driver provides a reduced current to drive the DQsignals to reduced voltages given the same loading of the data bus.

Although conventional memory devices, such as DDR SDRAM devices, allowlimited user programmability of the output impedance of data busterminals, they do not allow user programmability of the operating modeof the data bus terminals, including the establishment of preamble andpostamble conditions in the VDD mode, nor do they allow adjustment ofthe input or termination impedance when write data signals are beingcoupled to either the memory device or to another memory device that isconnected to a common bus.

There is therefore a need for a system and method to allow a user morecomplete programmability of the operating mode and impedance of memorydevice data bus terminals.

SUMMARY OF THE INVENTION

A memory device having a plurality of data bus terminals is programmedto control the operation of a memory device in either a first mode or asecond mode. The data bus terminals are biased to a first voltage whenwrite data signals are to be applied to the data bus terminals in thefirst operating mode. The data bus terminals are biased to a secondvoltage when write data signals are to be applied to the data busterminals in the second operating mode. When the memory device is tooutput read data signals, the data bus terminals are driven to either athird voltage or a fourth voltage in the first operating mode. In thesecond operating mode, the data bus terminals are driven to either afifth voltage or a sixth voltage when read data signals are to beapplied to the data bus terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a memory device according to oneembodiment of the invention.

FIG. 2 is a functional block diagram of a data bus terminal mode andimpedance control system according to one embodiment of the invention,which may be used in the memory device of FIG. 1.

FIG. 3 is a logic diagram showing one embodiment of an output enabletiming circuit that may be used in the data bus terminal mode andimpedance control system of FIG. 2.

FIG. 4 is a logic diagram showing one embodiment of a termination enabletiming circuit that may be used in the data bus terminal mode andimpedance control system of FIG. 2.

FIG. 5 is a logic diagram showing one embodiment of a clock timingcircuit that may be used in the data bus terminal mode and impedancecontrol system of FIG. 2.

FIG. 6 is a logic diagram showing one embodiment of a data timingcircuit that may be used in the data bus terminal mode and impedancecontrol system of FIG. 2.

FIG. 7 is a logic diagram showing one embodiment of pull-up logic thatmay be used in data terminal drive logic, which is part of the data busterminal mode and impedance control system of FIG. 2.

FIG. 8 is a logic diagram showing one embodiment of pull-down logic thatmay be used in data terminal drive logic, which is part of the data busterminal mode and impedance control system of FIG. 2.

FIG. 9 is a schematic diagram of one embodiment of a pull-up drivecircuit and a pull-down drive circuit that may be used in the data busterminal mode and impedance control system of FIG. 2.

FIG. 10 is a functional block diagram of a computer system that may usethe memory device of FIG. 2 or some other embodiment of a memory deviceusing various embodiments of the data bus terminal mode and impedancecontrol system according to the present invention.

DETAILED DESCRIPTION

FIG. 1 is a functional block diagram of a memory device including a databus terminal mode and impedance control system according to oneembodiment of the invention. The memory device is a double-data rate(DDR) synchronous dynamic random access memory (“SDRAM”) 2, although theprinciples described herein are particularly applicable to DDR II DRAMor any other memory device. The SDRAM 2 includes a command decoder 4that controls the operation of the SDRAM 2 responsive to high-levelcommand signals received on a control bus 6. These high level commandsignals, which are typically generated by a memory controller (not shownin FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chipselect signal CS*, a write enable signal WE*, a row address strobesignal RAS*, a column address strobe signal CAS*, and a data mask signalDQM, in which the “*” designates the signal as active low. The commanddecoder 4 generates a sequence of command signals responsive to the highlevel command signals to carry out the function (e.g., a read or awrite) designated by each of the high level command signals. The commanddecoder 4 also includes a mode register 8 that can be programmed byconventional means to select various operating modes in the SDRAM 2.According to one embodiment of the invention, the mode register 8 can beprogrammed to select the operating mode and impedance of data busterminals, which will be described in greater detail below.

The SDRAM 2 includes an address register 12 that receives row addressesand column addresses through an address bus 14. A row address isgenerally first received by the address register 12 and applied to a rowaddress multiplexer 18. The row address multiplexer 18 couples the rowaddress to a number of components associated with either of two memorybanks 20, 22 depending upon the state of a bank address bit forming partof the row address. Associated with each of the memory banks 20, 22 is arespective row address latch 26, which stores the row address, and a rowdecoder 28, which decodes the row address and applies correspondingsignals to one of the arrays 20 or 22. The row address multiplexer 18also couples row addresses to the row address latches 26 for the purposeof refreshing the memory cells in the arrays 20, 22. The row addressesare generated for refresh purposes by a refresh counter 30, which iscontrolled by a refresh controller 32. The refresh controller 32 is, inturn, controlled by the command decoder 4.

After the row address has been applied to the address register 12 andstored in one of the row address latches 26, a column address is appliedto the address register 12. The address register 12 couples the columnaddress to a column address latch 40. Depending on the operating mode ofthe SDRAM 2, the column address is either coupled through a burstcounter 42 to a column address buffer 44, or to the burst counter 42which applies a sequence of column addresses to the column addressbuffer 44 starting at the column address output by the address register12. In either case, the column address buffer 144 applies a columnaddress to a column decoder 48.

Data to be read from one of the arrays 20, 22 is coupled to columncircuitry 52, 54 for one of the arrays 20, 22, respectively. The data isthen coupled through a data output register 56 to data bus terminals 58.According to one embodiment of the invention, the data output register56 includes a data bus terminal mode and impedance control system 60that controls the operating mode and impedance of the data bus terminals58. More specifically, the mode register 8 in the command decoder 4 isprogrammed to operate the data output register 58 in either the CTT modeor a VDD mode described above. In both the CTT mode and the VDD mode,pull-up transistors (not shown in FIG. 1) are turned ON to couple thedata bus terminals to a supply voltage to output high read data signals,and pull-down transistors (not shown in FIG. 1) are turned ON to couplethe data bus terminals 58 to a ground to output low read data signals.However, the number of pull-up and pull-down transistors that are turnedON may vary between the two modes. The data bus terminal mode andimpedance control system 60 also selectively turns ON and OFF thepull-up and pull-down transistors in the data output register 56 whenread data signals are not being output from the SDRAM device 2. Morespecifically, in the VDD mode, a selected number of pull-up transistorsare turned ON to bias the data bus terminals 58 to a supply voltage whenwrite data signals are to be applied to the data bus terminals 58. Theselected number of pull-up transistors are preferably turned ON during apredetermined preamble time, such as one clock period before, and apredetermined postample time, such as one-half clock period after, writedata signals are to be applied to the data bus terminals 58. In the CTTmode, a selected number of pull-up transistors and a selected number ofpull-down transistors are turned ON to bias the data bus terminals 58 toone-half the supply voltage. The write data signals are coupled from thedata bus terminals 58 to a data input register 62, and from the datainput register 62 to one of the arrays 20, 22 through the columncircuitry 52, 54, respectively. A mask register 64 responds to a datamask DM signal to selectively alter the flow of data into and out of thecolumn circuitry 52, 54, such as by selectively masking data to be readfrom the arrays 20, 22. When neither read data signals are being outputfrom the SDRAM 2 nor write data signals are being input to the SDRAM 2,the data bus terminal mode and impedance control system 60 turns OFF thepull-up and pull-down transistors in the data output register 56.

FIG. 2 is a functional block diagram of a data bus terminal mode andimpedance control system 60 according to one embodiment of theinvention. The system 60 includes a timing circuit 80 that outputs afirst set of timing signals responsive to various transitions of a clockCLK signal when an OED signal transitions high. The timing circuit 80also outputs a second set of timing signals responsive to varioustransitions of the CLK signal when a GODT signal transitions high. Asexplained in greater detail below, the first set of timing signals isgenerated by an output enable timing circuit 82 to control the timing atwhich the data bus terminals 58 output read data responsive to the OEDsignal transitioning high. The second set of timing signals aregenerated by a termination enable timing circuit 84 to control thetiming at which the data bus terminals 58 are terminated with a selectedbias voltage and impedance when write data are to be input responsive toa GODT signal transitioning high.

The timing circuit 80 also includes a VDD mode timing circuit 88 thatgenerates a set of timing signals in the VDD mode but not in the CTTmode responsive to a VDDTERM signal, which is active high in the VDDmode, and various signals generated by the termination enable timingcircuit 84. The manner in which the VDD mode timing circuit 88 generatesthe timing signals will be explained in greater detail below.

The OED signal, the GODT signal and the VDDTERM signal are generated bythe command decoder 4 (FIG. 1) based on mode bits programmed into themode register 8 in the command decoder 4.

The first set of timing signals produced by the output enable timingcircuit 82 are combined with read data signals in a data timing circuit90. Basically, the data timing circuit 90 outputs four control signals,namely:

-   -   a first signal indicating that data that is valid responsive to        the rising edge of a clock signal has a high logic level;    -   a second signal indicating that data that is valid responsive to        the rising edge of a clock signal has a low logic level;    -   a third signal indicating that data that is valid responsive to        the falling edge of a clock signal has a high logic level; and    -   a fourth second signal indicating that data that is valid        responsive to the falling edge of a clock signal has a low logic        level.

The data bus terminal mode and impedance control system 60 furtherincludes data terminal drive logic 92 that receives the four controlsignals from the data timing circuit 90 as well as the second set ofsignals from the termination enable timing circuit 84 and the clocksignals from the clock timing circuit 88. The data terminal drive logic92 includes pull-up logic 94, which is active to drive or bias the databus terminals 58 high, and pull-down logic 96, which is active to driveor bias the data bus terminals 58 low. The pull-up logic 94 generatesactive low pull-up signals P0*, P1*, P2* that turn ON respective pull-uptransistors (not shown in FIG. 2). The pull-down logic 96 generatesactive high pull-down signals N0, N1, N2 that turn ON respectivepull-down transistors (not shown in FIG. 2).

One embodiment of the output enable timing circuit 82 in the timingcircuit 80 is shown in FIG. 3. As previously mentioned, the outputenable timing circuit 82 controls the timing at which the data busterminals 58 output read data signals. The output enable timing circuit82 contains a latch 104 having a data input terminal “D” to which anoutput data enable “OED” signal is applied and a clock input terminal towhich the clock “CLK” signal is applied. When the SDRAM device 2 isenabled to output read data signals, the OED signal transitions high,and a QE1 f signal (as used herein the suffix “f” designates the signalas the compliment of a signal not having the suffix) transitions low onthe next rising edge of the CLK signal, since the output of the latch istaken at the complimentary Qf output terminal. A QE1 signal at theoutput of an inverter 108 therefore transitions high on the rising edgeof the CLK signal following the OED signal transitioning high.

The QE2 signal at the output of the inverter 108 is applied to a secondlatch 110, which has a clock terminal receiving the compliment of theclock signal, CLKf. The Qf output of the latch 110 therefore transitionslow on the falling edge of the CLK signal, which causes a QE0 signal atthe output of an inverter 114 to transition high.

In operation, when the QED signal transitions high, the QE1 signaltransitions high on the next rising edge of the CLK signal, and the QE0signal then transitions high on the subsequent falling edge of the CLKsignal.

One embodiment of the termination enable timing circuit 84 in the timingcircuit 80 is shown in FIG. 4. As previously mentioned, the terminationenable timing circuit 84 controls the timing of the bias level andimpedance at the data bus terminals 58 when the SDRAM 2 is active butthe data bus terminals 58 are not outputting read data. The terminationenable timing circuit 84 includes a first latch 124 having a dataterminal to which a termination enable “GODT” signal is applied throughan inverter 128. When the GODT signal transitions high, the low at theoutput of the inverter 128 is clocked into the latch 124 on the nextrising edge of the CLK signal, to output a high ODTH0 signal at the Qfoutput of the latch 124. The complimentary ODTH0 f signal is obtained atthe output of an inverter 130 and applied to the data input of a secondlatch 134, which is clocked by the CLKf signal on the falling edge ofthe CLK signal. The latch 134 then outputs a high ODTL0 signal from itsQf output terminal. Therefore, in operation, when the GODT signaltransitions high, the ODTH0 signal transitions high on the next risingedge of the CLK signal. The ODTL0 signal at the output of the latch 134is applied to the input of an inverter 138, which outputs an ODTL0 fsignal. As explained in greater detail below, a low ODTL0 f signalcauses the data bus terminals 58 to be coupled to ground when read datasignals are not being applied to the data bus terminals 58.

The ODTL0 signal is also applied to one input of a NAND gate 140. Theother input of a NAND gate 140 receives a VDDTERMf signal, which is lowwhenever the mode register 8 (FIG. 1) has been programmed so that thememory device operates in the VDD mode. In operation in the CTT mode,the ODTL0 f signal transitions low responsive to the GODT signaltransitioning high following the rising edge and subsequent falling edgeof the clock signal. In the VDD mode, the ODTL0 f signal remains highand never transitions low.

FIG. 5 shows one embodiment of the clock timing circuit 88 in the timingcircuit 80, which generates a clock signal in the VDD mode but not inthe CTT mode. The clock timing circuit 88 includes an inverter 154 thatreceives a VDDTERM signal, which is active high whenever the moderegister has been programmed to operate in the VDD mode. The inverter154 generates a VDDTERMf signal, which is applied to an input of each oftwo NOR gates 158, 160. The NOR gates 158, 160 are disabled in the CTTmode when VDDTERM is low to produce low ODTH1 and ODTL1 signals,respectively. In the VDD mode when VDDTERM is high, the ODTH1 signal atthe output of the NOR gate 158 transitions high on the rising edge ofthe CLK signal following the GODT signal transitioning high, and theODTL1 signal at the output of the NOR gate 160 transitions high on thesubsequent falling edge of the CLK signal.

The signals produced by the output enable timing circuit 82 are combinedwith read data signals in the data timing circuit 90, an embodiment ofwhich is shown in FIG. 6. The data timing circuit 90 includes a NANDgate 174 and a NOR gate 176 that each receive a DR1 f signal, which hasa logic level that is the compliment of a data bit that is valid on therising edge of the CLK signal. The other input of the NAND gate 174receives the QE1 signal, which transitions active high to enable theNAND gate 174 on the rising edge of the CLK signal. The other input ofthe NOR gate 176 receives the QE1 f signal, which transitions low toenable the NOR gate 176 on the rising edge of the CLK signal. Thus, theNAND gate 174 and the NOR gate 176 are disabled to output a high QDNHfsignal and a low QUPH signal, respectively. The NAND gate 174 and theNOR gate 176 are enabled to generate QDNHf and QUPH signals,respectively, that are the compliment of the DR1 f signal responsive tothe rising edge of the CLK signal. Thus, when the NAND gate 174 and theNOR gate 176 are enabled, the QDNHf and QUPH signals have logic levelscorresponding to the logic level of the rising edge clock data signal.

In a similar manner, a NAND gate 180 and a NOR gate 182 each receive aDR0 f signal, which has a logic level that is the compliment of a databit that is valid on the falling edge of the CLK signal. The NAND gate180 and the NOR gate 182 receive the QE0 and QE0 f signal, respectively,so they are enabled on the falling edge of the CLK signal following theQED becoming active. As a result, they output QDNLf and QUPL signals,respectively, that are the compliment of the clock falling edgecomplimentary data signal DR0 f. Thus, when the NAND gate 180 and theNOR gate 182 are enabled, the QDNLf and QUPL signals have logic levelscorresponding to the logic level of the falling edge clock data signal.When the NAND gate 180 and the NOR gate 182 are disabled, they output ahigh QDNLf and a low QUPL signal, respectively.

One embodiment of the pull-up logic 94 used in the data terminal drivelogic 92 of FIG. 2 is shown in FIG. 7. As previously mentioned, thepull-up logic 94 generates signals that selectively drive or bias thedata bus terminals 58 high. The pull-up logic 94 includes a first set ofNOR gate 224, 226 having outputs that are coupled to cross-coupled passgates 228, 230, which are alternately enabled by complimentary CLK andCLK* signals. The outputs of the pass gates 228, 230 are coupled througha pair of inverters 234, 236 to generate the P0* signal. As explained ingreater detail below, when the P0* signal is active low, it turns ON aPMOS transistor to couple the data bus terminal to V_(CC).

The NOR gate 224 receives the QUPH signal, which corresponds to theclock rising edge data signal on the rising edge of the CLK signalfollowing the OED signal transitioning high. Thus, the QUPH signalcorresponds to a read data bit that is valid on the rising edge of theCLK signals. When the QUPH signal is not active, it remains low toenable the NOR gate 224. The NOR gate 224 also receives the ODTH0signal, which is generated by the latch 124. As previously explained,the ODTH0 signal transitions high on the rising edge of the CLK signalfollowing the termination signal GODT transitioning high. Otherwise theODTH0 signal is low to enable the NOR gate 124. As also previouslyexplained, the OED signal transitions high when read data signals are tobe output from the data bus terminals, and the GODT signal transitionshigh when write data signals are to be input through the data busterminals. Insofar as data are normally not being read from and writtento a memory device at the same time, either the OED or the GODT signal,but not both, normally transition high. Thus, the NOR gate 224 is eitherenabled by the low ODTH0 signal to output a timed clock leading edgeread data signal corresponding to the QUPH signal, or the NOR gate 224is enabled by the low QUPH signal to output a high clock leading edgetermination signal corresponding to the ODTH0 signal. Either of thesesignals is coupled to the PO* output terminal on the rising edge of theCLK signal.

The NOR gate 226 operates in a manner similar to the NOR gate 224 toeither output a data signal corresponding to the QUPL signal, which is aread data signal that is valid on the falling edge of the CLK signalsubsequent to QED transitioning high, or to output a termination signalcorresponding to the ODTL0 signal, which is a termination signal thattransitions high on the falling edge of the CLK signal following theGODT signal transitioning high. In either case, the output of the NORgate 226 is a data or termination signal that is valid on the fallingedge of the CLK signal, and it is coupled through the pass gate 230responsive to the falling edge of the CLK signal.

The pull-up logic 94 in the data terminal drive logic 92 also includes asecond set of NOR gate 240, 242 and a third set of NOR gates 246, 248,which operate similarly to the NOR gates 224, 226. The NOR gate 240,like the NOR gate 224, outputs a clock rising edge read data signalcorresponding to the QUPH signal on the rising edge of the CLK signalfollowing the OED signal transitioning high. The NOR gate 240 alsooutputs a clock rising edge termination signal. However, unlike the NORgate 224, which outputs the termination signal responsive to the ODTH0signal on the rising edge of the CLK signal following the GODT signaltransitioning high, the NOR gate 240 outputs the termination signal insuch circumstances only in the VDD mode. The signal at the output of theNOR gate 240, which is valid only on the rising edge of the CLK signal,is coupled through a pass gate 250, which is enabled on the rising edgeof the pass gate 250. Similarly, the signal at the output of the NORgate 242, which is valid only on the falling edge of the CLK signal, iscoupled through a pass gate 252, which is enabled on the falling edge ofthe pass gate 252. The outputs from the pass gates 250, 252 are coupledthrough a pair of inverters 256, 258 to a P1* output terminal.

The third set of NOR gates 246, 248 operate in substantially the samemanner as the NOR gates 224, 226 and 240, 242 in the data output modewhen read data are being coupled from the memory device. Morespecifically, the NOR gate 246 outputs a read data signal correspondingto the QUPH signal, which is valid on the rising edge of the CLK signalfollowing the OED signal transitioning high, and the NOR gate 248outputs a read data signal corresponding to the QUPL signal, which isvalid on the falling edge of the CLK signal following the OED signaltransitioning high. However, in the termination mode when write data areto be coupled to the data bus terminals, the NOR gates 246, 248 operatein a different manner. In particular, the NOR gates 246, 248 receive theVDDTERMf signal, which is high only in the CTT mode. In the VDD mode,the VDDTERMf signal simply enables the NOR gates 246, 248 so that theyfunction as inverters. The signal at the output of the NOR gate 246,which is valid only on the rising edge of the CLK signal, is coupledthrough a pass gate 260, which is enabled on the rising edge of the CLKsignal. The signal at the output of the NOR gate 248, which is validonly on the falling edge of the CLK signal, is coupled through a passgate 262, which is enabled on the falling edge of the CLK signal. Theoutputs from the pass gates 260, 262 are coupled through a pair ofinverters 266, 268 to a P2* output terminal.

FIG. 8 shows one embodiment of the pull-down logic 96 used in the dataterminal drive logic 92 of FIG. 2. As previously mentioned, thepull-down logic 96 generates signals that selectively drive or bias thedata bus terminals 58 low. More specifically, the pull-down logic 96includes three sets of logic circuits outputting three signals, N0, N1and N2, which are active high. The first set of logic circuits includesa pair of NAND gates 280, 282 coupled through respective pass-gates 286,288 to a pair of series connected inverters 290, 292 to produce the N0signal. The NAND gate 280 receives the QDNHf signal generated by theNAND gate 174, which has a logic level corresponding to the clock risingedge data. The logic level of the QDNHf signal is inactive high toenable the NAND gate 280 when the QE1 signal is low, which occurs eitheron the falling edge of the CLK signal or when the OED signal has nottransitioned high. Thus, the NAND gate 280 is enabled whenever thememory device is not active in outputting clock rising edge read data.The QDNHf signal corresponds to the clock leading edge read data signalresponsive to the rising edge of the CLK signal after the OED signal hastransitioned high. The signal at the output of the NAND gate 280 iscoupled through the pass gate 286 responsive to the leading edge of theCLK signal, and through the inverters 290, 292 to generate the N0signal. The NAND gate 280 also receives the ODTH0 f signal, which isgenerated at the output of the inverter 130. The ODTH0 f signal is lowon the rising edge of the CLK signal following the GODT signaltransitioning high. Thus, the NAND gate 280 outputs a high on the risingedge of the CLK signal when the data bus terminals are to be terminatedfor receiving write data signals.

The NAND gate 282 operates in a similar manner to output either a readdata signal or a termination signal after the falling edge of the CLKsignal. More specifically, the NAND gate 282 receives the QDNLf signal,which is generated by the NAND gate 180. The QDNLf signal corresponds tothe clock falling edge read data signal responsive to the falling edgeof the CLK signal after the OED signal has transitioned high. This readdata signal at the output of the NAND gate 282 is coupled through thepass gate 288 on the falling edge of the CLK signal to generate the N0signal. When a clock falling edge read data signal is not being output,the QDNLf signal is high to enable the NAND gate 282. The other input ofthe NAND gate 282 receives the ODTL0 f signal, which is generated by theNAND gate 140. The ODTL0 f signal is low only in the CTT mode only onthe falling edge of the CLK signal after the GODT signal has transitionhigh. At all other times, including at all times in the VDD mode, theODTL0 f signal is high to enable the NAND gate 282. Thus, the NAND gate282 outputs a high on the falling edge of the CLK signal in the CTT modewhen the data bus terminals are to be terminated for receiving writedata signals.

The N1 signal is generated from the QDNHf coupled through an inverter300, a pass gate 302 and a pair of inverters 306, 308 on the rising edgeof the CLK signal. The QDNHf signal is also applied to the NAND gate280, and it corresponds to the clock rising edge read data signal. TheN1 signal is also generated from the QDNLf signal, which is coupledthrough an inverter 310, a pass gate 312 and the inverters 306, 308 onthe falling edge of the CLK signal. The QDNLf signal is also applied tothe NAND gate 282, and it corresponds to the clock falling edge readdata signal. Thus, the N1 signal corresponds to the clock rising edgeread data signal responsive to the rising edge of the CLK signal and tothe clock falling edge read data signal responsive to the falling edgeof the CLK signal. The N1 signal is not generated at any time during thetermination period when write data signals are being applied to thememory device or the memory device is inactive.

The N2 signal is generated by inverters 320, 322, pass gates 326, 328and inverters 332, 334 from the QDNHf and QDNLf signals in the samemanner as the N1 signal is generated.

The final component in the data bus terminal mode and impedance controlsystem 80 are a pull-up drive circuit 340 and a pull-down drive circuit344, embodiments of which are shown in FIG. 9. The pull-up drive circuit340 includes three PMOS transistors 350, 352, 354 coupled in series withrespective resistors 360, 362, 364 between V_(CC) and the data busterminal 58. The gates of the PMOS transistors 350, 352, 354 receive theP0*, P1* and P2* signals, respectively. When any of the P0*, P1* and P2*signals is active low, the corresponding PMOS transistor 350, 352, 354is turned ON to drive the data bus terminal 58 to V_(CC). The number ofPMOS transistor 350, 352, 354 turned ON controls the output impedance atthe data bus terminal 58 when a high read data signal is being output.The number of PMOS transistor 350, 352, 354 turned ON in the VDD modealso controls the termination impedance at the data bus terminal 58 whena write data signal is being applied to the data bus terminal 58.

The pull-down drive circuit 344 includes three NMOS transistors 380,382, 384 coupled in series with respective resistors 390, 392, 394between ground and the data bus terminal 58. The gates of the NMOStransistors 380, 382, 384 receive the N0, N1 and N2 signals,respectively. When any of the N0, N1 and N2 signals is active high, thecorresponding NMOS transistor 380, 382, 384 is turned ON to drive thedata bus terminal 58 to ground. The number of NMOS transistor 380, 382,384 turned ON controls the output impedance at the data bus terminal 58when a low read data signal is being output. When one or more of thePMOS transistors 350, 352, 354 is turned ON at the same time one or moreof the NMOS transistors 380, 382, 384 is turned ON, the data busterminal 58 is biased to VCC/2. This situation occurs in the CTT modewhen a write data signal is being applied to the data bus terminal 58.The number of PMOS transistors 350, 352, 354 and NMOS transistors 380,382, 384 that are turned ON in the CTT mode controls the terminationimpedance at the data bus terminal 58 when a write data signal is beingapplied to the data bus terminal 58 in the CTT mode.

In operation, when the QED signal transitions high to output read datasignals, the PMOS transistors 350, 352, 354 and the NMOS transistors380, 382, 384 are turned OFF or ON so that the logic level at the databus terminal 58 corresponds to the read data signal on the rising andfalling edges of the CLK signal. In the CTT mode, the PMOS transistors350, 352, 354 are all turned ON when the read data signal is high. Inthe VDD mode, only the PMOS transistors 350 and 352 (but not the PMOStransistor 354) are all turned ON when the read data signal is high. Itis not necessary to turn the PMOS transistor 354 ON since the data busterminal 58 is biased high in the VDD mode. When the read data signal islow, all three of the NMOS transistors 380, 382, 384 are turned ON inboth the CTT mode and the VDD mode.

When write data signals are to be applied to the data bus terminal 58,the GODT signal transitions high. The PMOS transistors 350, 352, 354 andthe NMOS transistors 380, 382, 384 are then selectively turned OFF or ONseparately on both the rising and falling edge of the CLK signal tocontrol the bias voltage and impedance at the data bus terminal 58. Morespecifically, in the VDD mode, the PMOS transistors 350 and 352 areturned ON, and all of the NMOS transistors 380, 382, 384 are turned OFF.In the CTT mode, only the PMOS transistor 350 is turned ON, but the NMOStransistor 380 is also turned ON. By turning only one PMOS transistor350 and only one NMOS transistor 380 ON, the data bus terminal 58 isbiased to VCC/2, but relatively little current is consumed compared toif multiple of the PMOS transistors 350, 352, 354 and NMOS transistors380, 382, 384 were turned ON.

When neither write data signals are being applied to the SDRAM device 2and read data signals are not be output from the SDRAM device 2, boththe OED and the GODT signals remain low. Therefore, none of the PMOStransistors 350, 352, 354 and none of the NMOS transistors 380, 382, 384are turned ON.

The SDRAM device 2 shown in FIG. 1 can be used in various electronicsystems. For example, it may be used in a processor-based system, suchas a computer system 300 shown in FIG. 10. The computer system 300includes a processor 302 for performing various computing functions,such as executing specific software to perform specific calculations ortasks. The processor 302 includes a processor bus 304 that normallyincludes an address bus, a control bus, and a data bus. In addition, thecomputer system 300 includes one or more input devices 314, such as akeyboard or a mouse, coupled to the processor 302 to allow an operatorto interface with the computer system 300. Typically, the computersystem 300 also includes one or more output devices 316 coupled to theprocessor 302, such output devices typically being a printer or a videoterminal. One or more data storage devices 318 are also typicallycoupled to the processor 302 to allow the processor 302 to store data inor retrieve data from internal or external storage media (not shown).Examples of typical storage devices 318 include hard and floppy disks,tape cassettes, and compact disk read-only memories (CD-ROMs). Theprocessor 302 is also typically coupled to cache memory 326, which isusually static random access memory (“SRAM”), and to the SDRAM device 2through a memory controller 330. The memory controller 330 normallyincludes a control bus 336 and an address bus 338 that are coupled tothe SDRAM device 2. A data bus 340 is coupled from the SDRAM device 2 tothe processor bus 304 either directly (as shown), through the memorycontroller 330, or by some other means.

Although the present invention has been described with reference to thedisclosed embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention. Such modifications are well within the skillof those ordinarily skilled in the art. Accordingly, the invention isnot limited except as by the appended claims.

1. A method of controlling the operation of a memory device having aplurality of data bus terminals, the method comprising: biasing the databus terminals to a first voltage when write data signals are to beapplied to the data bus terminals in a first operating mode; biasing thedata bus terminals to a second voltage when write data signals are to beapplied to the data bus terminals in a second operating mode; andprogramming the memory device to operate in either the first operatingmode or the second operating mode.
 2. The method of claim 1, furthercomprising: driving the data bus terminals to either a third or a fourthvoltage when read data signals are to be applied to the data busterminals in the first operating mode; and driving the data busterminals to either a fifth or a sixth voltage when read data signalsare to be applied to the data bus terminals in the second operatingmode.
 3. The method of claim 2 wherein the first voltage is intermediatethe third and fourth voltages.
 4. The method of claim 3 wherein thesecond voltage is substantially equal to the fifth voltage.
 5. Themethod of claim 2 wherein the second voltage is substantially equal tothe fifth voltage.
 6. The method of claim 2 wherein the third voltage issubstantially equal to the fifth voltage.
 7. The method of claim 6wherein the third and fifth voltage is substantially equal to a supplyvoltage.
 8. The method of claim 2 wherein the fourth voltage issubstantially equal to the sixth voltage.
 9. The method of claim 8wherein the fourth and sixth voltage is substantially equal to groundpotential.
 10. The method of claim 1 wherein the act of biasing the databus terminals to a second voltage when write data signals are to beapplied to the data bus terminals in a second operating mode comprisesbiasing the data bus terminals to the second voltage for a preambleperiod before and a postamble period after write data signals areapplied to the data bus terminals in the second operating mode.
 11. Themethod of claim 10 wherein the memory device comprises a synchronousmemory device operating in synchronism with a received clock signal, andwherein the preamble period comprise one period of the clock signal andthe postamble period comprises one-half period of the clock signal. 12.The method of claim 1 wherein the memory device comprises a dynamicrandom access memory (“DRAM”) device.
 13. The method of claim 12 whereinthe DRAM device comprises a double data rate synchronous DRAM (“SDRAM”)device in which read data signals are output from and write data signalsare input to the SDRAM device responsive to both rising edges andfalling edges of a clock signal, and wherein the acts of biasing thedata bus terminals to a first or second voltage when write data signalsare to be applied to the data bus terminals in a first or secondoperating mode, respectively, comprises biasing the data bus terminalsto a first or second voltage responsive to both rising edges and fallingedges of the clock signal.
 14. The method of claim 1 wherein the memorydevice includes a programmable mode register, and wherein the act ofprogramming the memory device to operate in either the first operatingmode or the second operating mode comprises programming the moderegister to generate output signals indicative of either operation inthe first operating mode or operation in the second operating mode. 15.A method of controlling the operation of a memory device having aplurality of data bus terminals, the method comprising: driving the databus terminals to either a first or a second voltage when read datasignals are to be applied to the data bus terminals in a first operatingmode; and driving the data bus terminals to either a third or a fourthvoltage when read data signals are to be applied to the data busterminals in a second operating mode; and programming the memory deviceto operate in either the first operating mode or the second operatingmode.
 16. The method of claim 15 wherein the first voltage issubstantially equal to the third voltage.
 17. The method of claim 16wherein the first and third voltage is substantially equal to a supplyvoltage.
 18. The method of claim 15 wherein the second voltage issubstantially equal to the fourth voltage.
 19. The method of claim 18wherein the fourth and sixth voltage is substantially equal to groundpotential.
 20. The method of claim 15 wherein the memory devicecomprises a dynamic random access memory (“DRAM”) device.
 21. The methodof claim 20 wherein the DRAM device comprises a double data ratesynchronous DRAM (“SDRAM”) device in which read data signals are outputfrom and write data signals are input to the SDRAM device responsive toboth rising edges and falling edges of a clock signal, wherein the actsof driving the data bus terminals to either a first or a second voltagewhen read data signals are to be applied to the data bus terminals in afirst operating mode comprises driving the data bus terminals to eithera first or a second voltage responsive to both rising edges and fallingedges of the clock signal when read data signals are to be applied tothe data bus terminals in a first operating mode, and wherein the act ofdriving the data bus terminals to either a third or a fourth voltagewhen read data signals are to be applied to the data bus terminals in asecond operating mode comprises driving the data bus terminals to eithera third or a fourth voltage responsive to both rising edges and fallingedges of the clock signal when read data signals are to be applied tothe data bus terminals in a second operating mode.
 22. The method ofclaim 15 wherein the memory device includes a programmable moderegister, and wherein the act of programming the memory device tooperate in either the first operating mode or the second operating modecomprises programming the mode register to generate output signalsindicative of either operation in the first operating mode or operationin the second operating mode.
 23. A system for controlling the operationof a plurality of data bus terminals in a memory device, the systemcomprising: a mode register programmable to select either a first modeor a second mode of operation for the data bus terminals, the moderegister being operable to output a mode control signal corresponding tothe selected mode; a timing circuit coupled to receive the mode controlsignal from the mode register, the timing circuit receiving a clocksignal and generating timing signals corresponding to the selected oneof the first and second modes in synchronism with the clock signal; adata timing circuit coupled to the timing circuit, the data timingcircuit receiving read data signals and generating timed data signalscorresponding to the read data signals; data bus terminal drive logiccoupled to the data timing circuit, the data bus terminal drive logicgenerating output signals responsive to the timed data signals; andpull-up and pull-down circuitry coupled to the data bus terminal drivelogic, the pull-up and pull-down circuitry being operable to drive thedata bus terminals to either a first or a second voltage if the firstmode of operation is selected and to either a third or a fourth voltageif the second mode of operation is selected.
 24. The system of claim 23wherein the timing circuit is further operable to generate terminationtiming signals corresponding to the selected one of the first and secondmodes, and wherein the pull-up and pull-down circuitry is operable tobias the data bus terminals to a fifth voltage if the first mode ofoperation is selected or to a sixth voltage if the second mode ofoperation is selected.
 25. The system of claim 23 wherein the datatiming circuit is operable to generate timed data signals correspondingto the read data signals in synchronism with both a rising edge and afalling edge of the clock signal.
 26. The system of claim 23 wherein thetiming circuit comprises: an output enable timing circuit receiving theclock signal, the output enable timing circuit being operable togenerate output timing signals synchronized to the clock signalresponsive to an output enable signal; a termination enable timingcircuit receiving the clock signal, the termination enable timingcircuit being operable to generate termination timing signalssynchronized to the clock signal responsive to a termination initiationsignal; and a mode timing circuit coupled to the mode register toreceive the mode control signal, the mode timing circuit being operableto generate mode timing signals synchronized to the clock signal as afunction of the received mode control signal.
 27. The system of claim 26wherein the data timing circuit is coupled to receive the output timingsignals from the output enable timing circuit, the data timing circuitcoupled to the timing circuit, the data timing circuit being operable togenerating the timed data signals corresponding to the read data signalsin synchronism with the output timing signals.
 28. The system of claim27 wherein the pull-up circuitry comprises a first set of logic elementseach of which has a first input coupled to receive one of the timed datasignals from the data timing circuit and a second input coupled toreceive one of the termination timing signals from the terminationenable timing circuit, and wherein the pull-down circuitry comprises asecond set of logic elements each of which has a first input coupled toreceive one of the timed data signals from the data timing circuit and asecond input coupled to receive one of the termination timing signalsfrom the termination enable timing circuit, the pull-up circuitry beingoperable to drive the data bus terminals to the first voltage if thefirst mode of operation is selected and to the third voltage if thesecond mode of operation is selected, and the pull-down circuitry beingoperable to drive the data bus terminals to the second voltage if thefirst mode of operation is selected and to the fourth voltage if thesecond mode of operation is selected.
 29. The system of claim 28 whereinthe first voltage is substantially equal to the third voltage, and thesecond voltage is substantially equal to the fourth voltage.
 30. Thesystem of claim 29 wherein the first and third voltage is substantiallyequal to a supply voltage, and the second and fourth voltage issubstantially equal to ground.
 31. A memory device, comprising: a rowaddress circuit operable to receive and decode row address signalsapplied to external address terminals of the memory device; a columnaddress circuit operable to receive and decode column address signalsapplied to the external address terminals; an array of memory cellsoperable to store data written to and read from the array at a locationdetermined by the decoded row address signals and the decoded columnaddress signals; a write data path circuit operable to couple write datasignals from the external data bus terminals of the memory device and tocouple the write data signals the array; a command decoder operable todecode a plurality of command signals applied to respective externalcommand terminals of the memory device, the command decoder beingoperable to generate control signals corresponding to the decodedcommand signals, the command decoder including a mode registerprogrammable to select either a first mode or a second mode of operationfor the data bus terminals, the mode register being operable to output amode control signal corresponding to the selected mode; and a read datapath circuit operable to couple read data signals from the array to theexternal data bus terminals of the memory device, the read data pathcomprising: a timing circuit coupled to receive the mode control signalfrom the mode register, the timing circuit receiving a clock signal andgenerating timing signals corresponding to the selected one of the firstand second modes in synchronism with the clock signal; a data timingcircuit coupled to the timing circuit, the data timing circuit receivingread data signals and generating timed data signals corresponding to theread data signals; data bus terminal drive logic coupled to the datatiming circuit, the data bus terminal drive logic generating outputsignals responsive to the timed data signals; and pull-up and pull-downcircuitry coupled to the data bus terminal drive logic, the pull-up andpull-down circuitry being operable to drive the data bus terminals toeither a first or a second voltage if the first mode of operation isselected and to either a third or a fourth voltage if the second mode ofoperation is selected.
 32. The memory device of claim 31 wherein thetiming circuit is further operable to generate termination timingsignals corresponding to the selected one of the first and second modes,and wherein the pull-up and pull-down circuitry is operable to bias thedata bus terminals to a fifth voltage if the first mode of operation isselected or to a sixth voltage if the second mode of operation isselected.
 33. The memory device of claim 31 wherein the data timingcircuit is operable to generate timed data signals corresponding to theread data signals in synchronism with both a rising edge and a fallingedge of the clock signal.
 34. The memory device of claim 31 wherein thetiming circuit comprises: an output enable timing circuit receiving theclock signal, the output enable timing circuit being operable togenerate output timing signals synchronized to the clock signalresponsive to an output enable signal; a termination enable timingcircuit receiving the clock signal, the termination enable timingcircuit being operable to generate termination timing signalssynchronized to the clock signal responsive to a termination initiationsignal; and a mode timing circuit coupled to the mode register toreceive the mode control signal, the mode timing circuit being operableto generate mode timing signals synchronized to the clock signal as afunction of the received mode control signal.
 35. The memory device ofclaim 34 wherein the data timing circuit is coupled to receive theoutput timing signals from the output enable timing circuit, the datatiming circuit coupled to the timing circuit, the data timing circuitbeing operable to generating the timed data signals corresponding to theread data signals in synchronism with the output timing signals.
 36. Thememory device of claim 35 wherein the pull-up circuitry comprises afirst set of logic elements each of which has a first input coupled toreceive one of the timed data signals from the data timing circuit and asecond input coupled to receive one of the termination timing signalsfrom the termination enable timing circuit, and wherein the pull-downcircuitry comprises a second set of logic elements each of which has afirst input coupled to receive one of the timed data signals from thedata timing circuit and a second input coupled to receive one of thetermination timing signals from the termination enable timing circuit,the pull-up circuitry being operable to drive the data bus terminals tothe first voltage if the first mode of operation is selected and to thethird voltage if the second mode of operation is selected, and thepull-down circuitry being operable to drive the data bus terminals tothe second voltage if the first mode of operation is selected and to thefourth voltage if the second mode of operation is selected.
 37. Thememory device of claim 36 wherein the first voltage is substantiallyequal to the third voltage, and the second voltage is substantiallyequal to the fourth voltage.
 38. The memory device of claim 37 whereinthe first and third voltage is substantially equal to a supply voltage,and the second and fourth voltage is substantially equal to ground. 39.The memory device of claim 31 wherein the array of memory cells comprisean array of dynamic random access memory cells.
 40. A processor-basedsystem, comprising a processor having a processor bus; an input devicecoupled to the processor through the processor bus adapted to allow datato be entered into the computer system; an output device coupled to theprocessor through the processor bus adapted to allow data to be outputfrom the computer system; and a dynamic random access memory devicecoupled to the processor bus adapted to allow data to be stored, thedynamic random access memory device comprising: a row address circuitoperable to receive and decode row address signals applied to externaladdress terminals of the memory device; a column address circuitoperable to receive and decode column address signals applied to theexternal address terminals; an array of dynamic random access memorycells operable to store data written to and read from the array at alocation determined by the decoded row address signals and the decodedcolumn address signals; a write data path circuit operable to couplewrite data signals from the external data bus terminals of the memorydevice and to couple the write data signals the array; a command decoderoperable to decode a plurality of command signals applied to respectiveexternal command terminals of the memory device, the command decoderbeing operable to generate control signals corresponding to the decodedcommand signals, the command decoder including a mode registerprogrammable to select either a first mode or a second mode of operationfor the data bus terminals, the mode register being operable to output amode control signal corresponding to the selected mode; and a read datapath circuit operable to couple read data signals from the array to theexternal data bus terminals of the memory device, the read data pathcomprising: a timing circuit coupled to receive the mode control signalfrom the mode register, the timing circuit receiving a clock signal andgenerating timing signals corresponding to the selected one of the firstand second modes in synchronism with the clock signal; a data timingcircuit coupled to the timing circuit, the data timing circuit receivingread data signals and generating timed data signals corresponding to theread data signals; data bus terminal drive logic coupled to the datatiming circuit, the data bus terminal drive logic generating outputsignals responsive to the timed data signals; and pull-up and pull-downcircuitry coupled to the data bus terminal drive logic, the pull-up andpull-down circuitry being operable to drive the data bus terminals toeither a first or a second voltage if the first mode of operation isselected and to either a third or a fourth voltage if the second mode ofoperation is selected.
 41. The processor-based system of claim 40wherein the timing circuit is further operable to generate terminationtiming signals corresponding to the selected one of the first and secondmodes, and wherein the pull-up and pull-down circuitry is operable tobias the data bus terminals to a fifth voltage if the first mode ofoperation is selected or to a sixth voltage if the second mode ofoperation is selected.
 42. The processor-based system of claim 40wherein the data timing circuit is operable to generate timed datasignals corresponding to the read data signals in synchronism with botha rising edge and a falling edge of the clock signal.
 43. Theprocessor-based system of claim 40 wherein the timing circuit comprises:an output enable timing circuit receiving the clock signal, the outputenable timing circuit being operable to generate output timing signalssynchronized to the clock signal responsive to an output enable signal;a termination enable timing circuit receiving the clock signal, thetermination enable timing circuit being operable to generate terminationtiming signals synchronized to the clock signal responsive to atermination initiation signal; and a mode timing circuit coupled to themode register to receive the mode control signal, the mode timingcircuit being operable to generate mode timing signals synchronized tothe clock signal as a function of the received mode control signal. 44.The processor-based system of claim 43 wherein the data timing circuitis coupled to receive the output timing signals from the output enabletiming circuit, the data timing circuit coupled to the timing circuit,the data timing circuit being operable to generating the timed datasignals corresponding to the read data signals in synchronism with theoutput timing signals.
 45. The processor-based system of claim 44wherein the pull-up circuitry comprises a first set of logic elementseach of which has a first input coupled to receive one of the timed datasignals from the data timing circuit and a second input coupled toreceive one of the termination timing signals from the terminationenable timing circuit, and wherein the pull-down circuitry comprises asecond set of logic elements each of which has a first input coupled toreceive one of the timed data signals from the data timing circuit and asecond input coupled to receive one of the termination timing signalsfrom the termination enable timing circuit, the pull-up circuitry beingoperable to drive the data bus terminals to the first voltage if thefirst mode of operation is selected and to the third voltage if thesecond mode of operation is selected, and the pull-down circuitry beingoperable to drive the data bus terminals to the second voltage if thefirst mode of operation is selected and to the fourth voltage if thesecond mode of operation is selected.
 46. The processor-based system ofclaim 45 wherein the first voltage is substantially equal to the thirdvoltage, and the second voltage is substantially equal to the fourthvoltage.
 47. The processor-based system of claim 46 wherein the firstand third voltage is substantially equal to a supply voltage, and thesecond and fourth voltage is substantially equal to ground.